Nonvolatile memory devices include flash EEPROMs (electrical erasable programmable read only memory devices). FIG. 1 represents the relevant portion of a typical flash memory cell 10. The memory cell 10 typically includes a source region 12, a drain region 14 and a channel region 16 in a substrate 18; and a stacked gate structure 20 overlying the channel region 16. The stacked gate 20 includes a thin gate dielectric layer 22 (commonly referred to as the tunnel oxide) formed on the surface of the substrate 18. The stacked gate 20 also includes a polysilicon floating gate 24 which overlies the tunnel oxide 22 and an interpoly dielectric layer 26 which overlies the floating gate 24. The interpoly dielectric layer 26 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers 26a and 26b sandwiching a nitride layer 26c. Lastly, a polysilicon control gate 28 overlies the interpoly dielectric layer 26. The channel region 16 of the memory cell 10 conducts current between the source region 12 and the drain region 14 in accordance with an electric field developed in the channel region 16 by the stacked gate structure 20.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate "hot" (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage (V.sub.th) of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent "read" mode. The magnitude of the read current is used to determine whether a flash memory cell is programmed or not. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain of the respective memory cell.
Referring again to FIG. 1, conventional source erase operations for the flash memory cell 10 operate in the following manner. The memory cell 10 is programmed by applying a relatively high voltage V.sub.G (e.g., approximately 12 volts) to the control gate 28 and a moderately high voltage V.sub.D (e.g., approximately 9 volts) to the drain region 14 in order to produce "hot" electrons in the channel region 16 near the drain region 14. The hot electrons accelerate across the tunnel oxide 22 and into the floating gate 24 and become trapped in the floating gate 24 since the floating gate 24 is surrounded by insulators (the interpoly dielectric 26 and the tunnel oxide 22). As a result of the trapped electrons, the threshold voltage of the memory cell 10 increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the memory cell 10 created by the trapped electrons causes the cell to be programmed.
To read the flash memory cell 10, a predetermined voltage V.sub.G that is greater than the threshold voltage of an unprogrammed cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 28. If the memory cell 10 conducts, then the memory cell 10 has not been programmed (the cell 10 is therefore at a first logic state, e.g., a zero "0"). Likewise, if the memory cell 10 does not conduct, then the memory cell 10 has been programmed (the cell 10 is therefore at a second logic state, e.g., a one "1"). Consequently, it is possible to read each cell 10 to determine whether it has been programmed (and therefore identify its logic state).
In order to erase the flash memory cell 10, a relatively high voltage V.sub.S (e.g., approximately 12 volts) is applied to the source region 12 and the control gate 28 is held at a ground potential (V.sub.G =0), while the drain region 14 is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 22 between the floating gate 24 and the source region 12. The electrons that are trapped in the floating gate 24 flow toward and cluster at the portion of the floating gate 24 overlying the source region 22 and are extracted from the floating gate 24 and into the source region 12 by way of Fowler-Nordheim tunneling through the tunnel oxide 22. Consequently, as the electrons are removed from the floating gate 24, the memory cell 10 is erased.
There are advantages associated with a source erase operation compared to a channel erase operation. For example, a narrower erase distribution is associated with using a high positive voltage at the source region. Moreover, the source erase operation is insensitive to defects in the channel region since all tunneling occurs through the overlap region of the source region and the stacked gate (the floating gate in particular). However, a number of problems are associated with the source erase operation.
As a result of conventional fabrication techniques, the floating gate typically displays the effects of a "smiling face" phenomenon. For a number of reasons, some of which are understood and some of which are not understood, the bottom surface of the floating gate is rounded at the outer extremities. This phenomenon is illustrated in FIG. 2 (corresponding elements relative to FIG. 1 have corresponding reference numbers) which is an exploded view of FIG. 1. Referring to FIG. 2, a flash memory cell 10 including a substrate 18 is shown having thereon a tunnel oxide 22, a floating gate 24 over the tunnel oxide, an interpoly dielectric layer 26 over the floating gate 22, and a control gate 28 over the interpoly dielectric layer 26. Also shown are a drain region 14, a source region 12 and a channel region 16. Within the overlapped area 30, between the floating gate 24 and the source region, the "smiling face" phenomenon is illustrated. The "smiling face" phenomenon is characterized by a curvature at the bottom, outer edges of the floating gate which decreases overlap between the floating gate and the source region. Occurrence of the "smiling face" phenomenon lowers the efficiency of the erase operation because the area of overlap between the floating gate 24 and the source region 12 is undesirably decreased.
Another problem associated with conventional flash memory fabrication techniques is characterized by a small number of large oxide valley formations under the floating gate which cause nonuniform erase speed (thus a wide erase distribution). The problem of oxide valley formations is illustrated in FIG. 3 (corresponding elements relative to FIG. 2 have corresponding reference numbers) which is an exploded view of FIG. 2. In FIG. 3, the overlap area between the floating gate 24 and the source region 12 has an undesirably small number of relatively large oxide valley formations 32. Erase speed is higher in the oxide valley formations due to barrier height reduction and/or electron trap formation by the dopant of the floating gate.
In view of the aforementioned problems, there is a need for flash memory cells and methods of making such memory cells which permit efficient erasure operations while minimizing such problems associated with conventional flash memory cells and conventional fabrication techniques.